SUMMARY: UE3500 won't Boot, How do I Stop-N on VT Console?

From: Caparroso, Nelson T. (AAS) <Nelson.T.Caparroso_at_sbcdo.com>
Date: Fri Feb 22 2002 - 17:24:02 EST
Okay... my hunch my correct that I had a hosed NVRAM/OBP and needed to do an
L1-N or Stop-N. I never imagined that the NTI KVM Switch that we have does
not pass the Stop-N signal to the server. I had to attach directly a Sun KB
-- and while pressing Stop-N, turned on the server and did have me my Ok
prompt. I also did manage to find the command ... finaly remembered..
"sifting clock..."  I also updated my OBP which was rather old --  circa
last century.!


Thanks to all who've responded.




>  -----Original Message-----
> After applying a patch cluster to a UE3500 who've been complaining about
> TOD not matching the I/O boards - it won't boot any more. So I reckoned
> maybe my nvram should be reset by doin a Stop-N via the Sun KB/Monitor ---
> to no avail. So I tried hooking up a VT terminal to ttyA and managed to
> capture what's going on and seems like the final message was just
> "Evaluating:" apart from from the TOD message. I tuned on full diags
> switch and captured the following. SUN is saying a number of possibilities
> ... I think its just a NVRAM issue...  Any ideass?
> 
> 
> ------------------
> Clock board TOD does not match TOD on any IO board.
> Evaluating: Software Power ON
> Clock board TOD does not match TOD on any IO board.
> Evaluating: Hardware Power ON
> 7,0>
> 
> 7,0>@(#) POST 3.9.24 1999/12/23 17:35
> 
> 7,0>
> 
>     SelfTest Initializing (Diag Level 10, ENV 0000ff00) IMPL 0011 MASK 20
> 
> 7,0>Board 7 CPU FPROM Test
> 
> 7,0>Board 7 Basic CPU Test
> 
> 7,0>    Set CPU UPA Config and Init SDB Data
> 
> 7,0>	SRAM Mode = 22, Clock Mode = 4:1, PCON = 6fa, MCAP = 0
> 
> 7,0>Board 7 MMU Enable Test
> 
> 7,0>    DMMU Init
> 
> 7,0>    IMMU Init
> 
> 7,0>    Mapping Selftest Enabling MMUs
> 
> 7,0>Board 7 Ecache Test
> 
> 7,0>    Ecache Probe
> 
> 7,0>    Ecache Tags
> 
> 7,0>    Ecache Quick Verify
> 
> 7,0>    Ecache Init
> 
> 7,0>    Ecache RAM
> 
> 7,0>    Ecache Address Line
> 
> 7,0>    Configure Ecache Limit
> 
> 7,0>Ecache Size = 00400000,  Limited to 00400000 
> 
> 7,0>Board 7 FPU Functional Test
> 
> 7,0>    FPU Enable
> 
> 7,0>Board 7 Board Master Select Test
> 
> 7,0>    Selecting a Board Master
> 
> 7,0>Board 7 FireHose Devices Test
> 
> 7,0>Board 7 Address Controller Test
> 
> 7,0>    AC Initialization
> 
> 7,0>    AC DTAG Init
> 
> 7,0>Board 7 Dual Tags Test
> 
> 7,0>    AC DTAG Init
> 
> 7,0>Board 7 FireHose Controller Test
> 
> 7,0>    FHC Initialization
> 
> 7,0>Board 7 JTAG Test
> 
> 7,0>    Verify System Board Scan Ring
> 
> 7,0>Board 7 Centerplane Test
> 
> 7,0>    Centerplane Join
> 
> 7,0>Setting JTAG Master
> 
> 7,0>Clear JTAG Master
> 
> 7,0>Board 7 Setup Cache Size Test
> 
> 7,0>    Setting Up Cache Size
> 
> 7,0>Board 7 System Master Select Test
> 
> 7,0>    Setting System Master
> 
> 7,0>POST Master Selected (JTAG,CENTRAL)
> 
> 7,0>Board 16 Clock Board Test
> 
> 7,0>    Clock Board Initialization
> 
> 7,0>    Clock Board Temperature Check
> 
> 7,0>Board 16 Clock Board Serial Ports Test
> 
> 7,0>Board 16 NVRAM Devices Test
> 
> 7,0>    M48T59 (TOD) Init
> 
> 7,0>Board 7 System Board Probe  Test
> 
> 7,0>    Probing all CPU/Memory BDA
> 
> 7,0>    Probing System Boards
> 
> 7,0>    Probing CPU Module JTAG Rings
> 
> 7,0>Setting System Clock Frequency
> 
> 7,0>	CPU Module mid 14 Checked in OK (speed code = 7)
> 
> 7,0>	CPU mid 18 Version=00170011.20000507
> 
> 7,0>	CPU Module mid 18 Checked in OK (speed code = 7)
> 
> 7,0>	CPU mid 19 Version=00170011.20000507
> 
> 7,0>	CPU Module mid 19 Checked in OK (speed code = 7)
> 
> 7,0> ******** Clock Reset - retesting 
> 
> 7,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
> 
> 7,0>
> 
> 7,0>@(#) POST 3.9.24 1999/12/23 17:35
> 
> 7,0>
> 
>     SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK 20
> 
> 7,0>Board 7 CPU FPROM Test
> 
> 7,0>    CPU/Memory Board FPROM Checksum Test
> 
> 7,0>Board 7 Basic CPU Test
> 
> 7,0>    FPU Registers and Data Path Test
> 
> 7,0>    Instruction Cache Tag RAM Test
> 
> 7,0>    Instruction Cache Instruction RAM Test
> 
> 7,0>    Instruction Cache Next Field RAM Test
> 
> 7,0>    Instruction Cache Pre-decode RAM Test
> 
> 7,0>    Data Cache RAM Test
> 
> 7,0>    Data Cache Tags Test
> 
> 7,0>    DMMU Registers Access Test
> 
> 7,0>    DMMU TLB DATA RAM Access Test
> 
> 7,0>    DMMU TLB TAGS Access Test
> 
> 7,0>    IMMU Registers Access Test
> 
> 7,0>    IMMU TLB DATA RAM Access Test
> 
> 7,0>    IMMU TLB TAGS Access Test
> 
> 7,0>    Set CPU UPA Config and Init SDB Data
> 
> 7,0>	SRAM Mode = 22, Clock Mode = 4:1, PCON = 6fa, MCAP = 0
> 
> 7,0>Board 7 MMU Enable Test
> 
> 7,0>    DMMU Init
> 
> 7,0>    IMMU Init
> 
> 7,0>    Mapping Selftest Enabling MMUs
> 
> 7,0>Board 7 Ecache Test
> 
> 7,0>    Ecache Probe
> 
> 7,0>    Ecache Tags
> 
> 7,0>    Ecache Quick Verify
> 
> 7,0>    Ecache Init
> 
> 7,0>    Ecache RAM
> 
> 7,0>    Ecache 6N RAM Pattern Test
> 
> 7,0>    Ecache Address Line
> 
> 7,0>    Configure Ecache Limit
> 
> 7,0>Ecache Size = 00400000,  Limited to 00400000 
> 
> 7,0>Board 7 FPU Functional Test
> 
> 7,0>    FPU Enable
> 
> 7,0>Board 7 Board Master Select Test
> 
> 7,0>    Selecting a Board Master
> 
> 7,0>Board 7 FireHose Devices Test
> 
> 7,0>    PROM Datapath Test
> 
> 7,0>    FHC CPU SRAM Test
> 
> 7,0>Board 7 Address Controller Test
> 
> 7,0>    AC Registers Test
> 
> 7,0>    AC Initialization
> 
> 7,0>    Memory Registers  Test
> 
> 7,0>    Memory Registers Initialization Test
> 
> 7,0>    AC DTAG Init
> 
> 7,0>Board 7 Dual Tags Test
> 
> 7,0>    AC DTAG Test
> 
> 7,0>    AC DTAG Init
> 
> 7,0>Board 7 FireHose Controller Test
> 
> 7,0>    FHC Initialization
> 
> 7,0>Board 7 JTAG Test
> 
> 7,0>    Verify System Board Scan Ring
> 
> 7,0>Board 7 Centerplane Test
> 
> 7,0>    Centerplane and Arbiter Check Test
> 
> 7,0>Setting JTAG Master
> 
> 7,0>Clear JTAG Master
> 
> 7,0>    Centerplane Join
> 
> 7,0>Setting JTAG Master
> 
> 7,0>Clear JTAG Master
> 
> 7,0>Board 7 Setup Cache Size Test
> 
> 7,0>    Setting Up Cache Size
> 
> 7,0>Board 7 System Master Select Test
> 
> 7,0>    Setting System Master
> 
> 7,0>POST Master Selected (JTAG,CENTRAL)
> 
> 7,0>Board 16 Clock Board Test
> 
> 7,0>    Clock Board Registers Test
> 
> 7,0>    Clock Board Initialization
> 
> 7,0>    Clock Board Temperature Check
> 
> 7,0>Board 16 Clock Board Serial Ports Test
> 
> 7,0>    85C30 Register Test
> 
> 7,0>    85C30 Serial Ports Test
> 
> 7,0>	Keyboard Loopback
> 
> 7,0>	Mouse Loopback
> 
> 7,0>	Serial Port B Loopback
> 
> 7,0>	Remote Serial Port A Loopback
> 
> 7,0>	Remote Serial Port B Loopback
> 
> 7,0>Board 16 NVRAM Devices Test
> 
> 7,0>    M48T59 (TOD) Init
> 
> 7,0>    M48T59 (TOD) Functional Part 1 Test
> 
> 7,0>    NVRAM(Non-Destructive) Test
> 
> 7,0>Board 7 System Board Probe  Test
> 
> 7,0>    Probing all CPU/Memory BDA
> 
> 7,0>    Probing System Boards
> 
> 7,0>    Probing CPU Module JTAG Rings
> 
> 7,0>Setting System Clock Frequency
> 
> 7,0>	CPU Module mid 14 Checked in OK (speed code = 7)
> 
> 7,0>	CPU mid 18 Version=00170011.20000507
> 
> 7,0>	CPU Module mid 18 Checked in OK (speed code = 7)
> 
> 7,0>	CPU mid 19 Version=00170011.20000507
> 
> 7,0>	CPU Module mid 19 Checked in OK (speed code = 7)
> 
> 7,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
> 
> 7,0>TESTING BOARD 1
> 
> 7,0>Board 1 JTAG Test
> 
> 7,0>    Verify System Board Scan Ring
> 
> 7,0>Board 1 Centerplane Test
> 
> 7,0>    Centerplane Check
> 
> 7,0>Board 1 Address Controller Test
> 
> 7,0>    AC Registers Test
> 
> 7,0>    AC Initialization
> 
> 7,0>Setting Freq to 25MHZ
> 
> 7,0>    Memory Registers  Test
> 
> 7,0>    Memory Registers Initialization Test
> 
> 7,0>    AC DTAG Init
> 
> 7,0>Board 1 FireHose Controller Test
> 
> 7,0>    FHC Initialization
> 
> 7,0>Board 1 NVRAM Devices Test
> 
> 7,0>    M48T59 (TOD) Init
> 
> 7,0>    M48T59 (TOD) Functional Part 1 Test
> 
> 7,0>    NVRAM(Non-Destructive) Test
> 
> 7,0>TESTING BOARD 3
> 
> 7,0>Board 3 JTAG Test
> 
> 7,0>    Verify System Board Scan Ring
> 
> 7,0>Board 3 Centerplane Test
> 
> 7,0>    Centerplane Check
> 
> 7,0>Board 3 Address Controller Test
> 
> 7,0>    AC Registers Test
> 
> 7,0>    AC Initialization
> 
> 7,0>Setting Freq to 25MHZ
> 
> 7,0>    Memory Registers  Test
> 
> 7,0>    Memory Registers Initialization Test
> 
> 7,0>    AC DTAG Init
> 
> 7,0>Board 3 FireHose Controller Test
> 
> 7,0>    FHC Initialization
> 
> 7,0>Board 3 NVRAM Devices Test
> 
> 7,0>    M48T59 (TOD) Init
> 
> 7,0>    M48T59 (TOD) Functional Part 1 Test
> 
> 7,0>    NVRAM(Non-Destructive) Test
> 
> 7,0>Re-mapping to Local Device Space
> 
> 7,0>Begin Central Space Serial Port access
> 
> 7,0>Enable AC Control Parity
> 
> 7,0>Hotplug Trigger Test
> 
> 7,0>Init Counters for Hotplug
> 
> 7,0>Board 7 Cross Calls Test
> 
> 7,0>    Cross Calls Test
> 
> 7,0>Displaying PROM Versions
> 
> 7,0>Slot 1 IO Type 4    FCODE 1.8.24 1999/12/23 17:30  iPOST 3.4.24
> 1999/12/23 17:34
> 
> 7,0>Slot 3 IO Type 4    FCODE 1.8.24 1999/12/23 17:30  iPOST 3.4.24
> 1999/12/23 17:34
> 
> 7,0>Slot 7 CPU/Memory   OBP   3.2.24 1999/12/23 17:31  POST  3.9.24
> 1999/12/23 17:35
> 
> 7,0>Slot 9 CPU/Memory   OBP   3.2.24 1999/12/23 17:31  POST  3.9.24
> 1999/12/23 17:35
> 
> 7,0>Board 7 Environmental Probe Test
> 
> 7,0>    Environmental Probe
> 
> 7,0>Checking Power Supply Configuration
> 
> 7,0>Power is more than adequate, load 4 ps 3
> 
> 7,0>Reconfig memory due to POR or CLOCK RESET
> 
> 7,0>Reconfig memory due to DIAG_LEVEL
> 
> 7,0>Board 7 Probing Memory SIMMS Test
> 
> 7,0>    Probe SIMMID
> 
> 7,0>	Populated Memory Bank Status
> 
> 7,0>		bd #	Size	Address	Way	Status
> 
> 7,0>		7	256			Normal
> 
> 7,0>		7	256			Normal
> 
> 7,0>		9	256			Normal
> 
> 7,0>		9	256			Normal
> 
> 7,0>Board 7 Memory Configuration Test
> 
> 7,0>    Memory Interleaving
> 
> 7,0>	Total banks with 8MB SIMMs = 0
> 
> 7,0>	Total banks with 32MB SIMMs = 4
> 
> 7,0>	Total banks with 128MB SIMMs = 0
> 
> 7,0>	Total banks with 256MB SIMMs = 0
> 
> 7,0>	Overall memory default speed = 60ns
> 
> 7,0>Do OPTIMAL INTLV
> 
> 7,0>	Board 7 AC rev 5 RCTIME = 0 (Tras 71)
> 
> 7,0>	Board 9 AC rev 5 RCTIME = 0 (Tras 71)
> 
> 7,0>	Board 7 AC rev 5 RCTIME = 0 (Tras 71)
> 
> 7,0>	Board 9 AC rev 5 RCTIME = 0 (Tras 71)
> 
> 7,0>    Memory Refresh Enable
> 
> 7,0>Board 7 SIMMs Test
> 
> 7,0>    MP Memory SIMM Clear Test
> 
> 7,0>	Memory Size is 1024Mbytes
> 
> 7,0>	  CPU MID 18 clearing 00000000.00004000 to 00000000.15500000
> 
> 7,0>	  CPU MID 19 clearing 00000000.15500000 to 00000000.2aa00000
> 
> 7,0>	  CPU MID 14 clearing 00000000.2aa00000 to 00000000.40000000
> 
> 7,0>	  CPU MID 14 clearing 00000000.00000000 to 00000000.00004000
> 
> 7,0>    Memory Walking Rows and Columns Test
> 
> 7,0>    MP Memory SIMM (6N RAM Patterns) Test
> 
> 7,0>	Memory Size is 1024Mbytes
> 
> 7,0>	  CPU MID 18 testing 00000000.00000000 to 00000000.15500000
> 
> 7,0>	  CPU MID 19 testing 00000000.15500000 to 00000000.2aa00000
> 
> 7,0>	  CPU MID 14 testing 00000000.2aa00000 to 00000000.40000000
> 
> 7,0>    MP Memory SIMM (moving inverse) Test
> 
> 7,0>	Memory Size is 1024Mbytes
> 
> 7,0>	  CPU MID 18 testing 00000000.00000000 to 00000000.15500000
> 
> 7,0>	  CPU MID 19 testing 00000000.15500000 to 00000000.2aa00000
> 
> 7,0>	  CPU MID 14 testing 00000000.2aa00000 to 00000000.40000000
> 
> 7,0>Slave CPU Functional Tests
> 
> 7,0>	 Slave CPU MID 18 started
> 
> 9,0>Board 9 Functional CPU 0 Test
> 
> 9,0>    Dcache Init
> 
> 9,0>    Dcache Enable Test
> 
> 9,0>    Dcache Functionality Test
> 
> 9,0>    Ecache Stress Test
> 
> 9,0>    Ecache Functional Test
> 
> 9,0>    CPU Dispatch (Multi-Scalar) Test
> 
> 9,0>    SPARC Atomic Instructions Test
> 
> 9,0>    SPARC Prefetch Instructions Test
> 
> 9,0>    CPU Softint Registers and Interrupts Test
> 
> 9,0>    Uni-Processor Cache Coherence Test
> 
> 9,0>    Branch Memory Test
> 
> 9,0>    SDB ECC CE Test
> 
> 9,0>    SDB ECC Uncorrectable Test
> 
> 9,0>    FPU Instruction Test
> 
> 7,0>	 Slave CPU MID 19 started
> 
> 9,1>Board 9 Functional CPU 1 Test
> 
> 9,1>    Dcache Init
> 
> 9,1>    Dcache Enable Test
> 
> 9,1>    Dcache Functionality Test
> 
> 9,1>    Ecache Stress Test
> 
> 9,1>    Ecache Functional Test
> 
> 9,1>    CPU Dispatch (Multi-Scalar) Test
> 
> 9,1>    SPARC Atomic Instructions Test
> 
> 9,1>    SPARC Prefetch Instructions Test
> 
> 9,1>    CPU Softint Registers and Interrupts Test
> 
> 9,1>    Uni-Processor Cache Coherence Test
> 
> 9,1>    Branch Memory Test
> 
> 9,1>    SDB ECC CE Test
> 
> 9,1>    SDB ECC Uncorrectable Test
> 
> 9,1>    FPU Instruction Test
> 
> 7,0>Board 7 Functional CPU 0 Test
> 
> 7,0>    Dcache Init
> 
> 7,0>    Dcache Enable Test
> 
> 7,0>    Dcache Functionality Test
> 
> 7,0>    Ecache Stress Test
> 
> 7,0>    Ecache Functional Test
> 
> 7,0>    CPU Dispatch (Multi-Scalar) Test
> 
> 7,0>    SPARC Atomic Instructions Test
> 
> 7,0>    SPARC Prefetch Instructions Test
> 
> 7,0>    CPU Softint Registers and Interrupts Test
> 
> 7,0>    Uni-Processor Cache Coherence Test
> 
> 7,0>    Branch Memory Test
> 
> 7,0>    SDB ECC CE Test
> 
> 7,0>    SDB ECC Uncorrectable Test
> 
> 7,0>    FPU Instruction Test
> 
> 7,0>TESTING IO BOARD 1
> 
> 7,0>Board 1 I/O FPROM Test
> 
> 7,0>    I/O Board EPROM checksum Test
> 
> 7,0>@(#) iPOST 3.4.24 1999/12/23 17:34
> 
> 7,0> TESTING IO BOARD 1 ASICs
> 
> 7,0> TESTING SysIO Port 0
> 
> 7,0>Board 1 SysIO Registers Test
> 
> 7,0>    SysIO Register Initialization
> 
> 7,0>    IOMMU Registers and RAM Test
> 
> 7,0>    Streaming Buffer Registers and RAM Test
> 
> 7,0>    SBus Control and Config Registers Test
> 
> 7,0>    SysIO RAM Initialization
> 
> 7,0>Board 1 SysIO Functional Test
> 
> 7,0>    Clear Interrupt Map and State Registers
> 
> 7,0>    SysIO Interrupts  Test
> 
> 7,0>    SysIO Timers/Counters Test
> 
> 7,0>    IOMMU Virtual Address TLB Tag Compare Test
> 
> 7,0>    Streaming Buffer Flush Test
> 
> 7,0>    DMA Merge Buffer Test
> 
> 7,0>    SYSIO ECC Correctable Test
> 
> 7,0>    SYSIO ECC UnCorrectable Test
> 
> 7,0>    SysIO Sbus Probe Test
> 
> 7,0>    SysIO Register Initialization Test
> 
> 7,0>    SysIO RAM Initialization Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0>Board 1 OnBoard IO Chipset (SOC) Test
> 
> 7,0>    SOC SRAM Test
> 
> 7,0>    SOC Registers Test
> 
> 7,0>    SOC Interrupt Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0> TESTING SysIO Port 1
> 
> 7,0>Board 1 SysIO Registers Test
> 
> 7,0>    SysIO Register Initialization
> 
> 7,0>    IOMMU Registers and RAM Test
> 
> 7,0>    Streaming Buffer Registers and RAM Test
> 
> 7,0>    SBus Control and Config Registers Test
> 
> 7,0>    SysIO RAM Initialization
> 
> 7,0>Board 1 SysIO Functional Test
> 
> 7,0>    Clear Interrupt Map and State Registers
> 
> 7,0>    SysIO Interrupts  Test
> 
> 7,0>    SysIO Timers/Counters Test
> 
> 7,0>    IOMMU Virtual Address TLB Tag Compare Test
> 
> 7,0>    Streaming Buffer Flush Test
> 
> 7,0>    DMA Merge Buffer Test
> 
> 7,0>    SYSIO ECC Correctable Test
> 
> 7,0>    SYSIO ECC UnCorrectable Test
> 
> 7,0>    SysIO Sbus Probe Test
> 
> 7,0>    SysIO Register Initialization Test
> 
> 7,0>    SysIO RAM Initialization Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0>Board 1 OnBoard IO Chipset (FEPS) Test
> 
> 7,0>    FAS366 Registers Test
> 
> 7,0>    ESP FAS366 DVMA burst mode read/write Test
> 
> 7,0>    FAS366 FIFO TO DMA Test
> 
> 7,0>    DMA TO FAS366 FIFO Test
> 
> 7,0>    FEPS (Ethernet) Registers Test
> 
> 7,0>    FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test
> 
> 7,0>    SysIO Register Initialization Test
> 
> 7,0>    SysIO RAM Initialization Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0>IO BOARD 1 TESTED
> 
> 7,0>TESTING IO BOARD 3
> 
> 7,0>Board 3 I/O FPROM Test
> 
> 7,0>    I/O Board EPROM checksum Test
> 
> 7,0>@(#) iPOST 3.4.24 1999/12/23 17:34
> 
> 7,0> TESTING IO BOARD 3 ASICs
> 
> 7,0> TESTING SysIO Port 0
> 
> 7,0>Board 3 SysIO Registers Test
> 
> 7,0>    SysIO Register Initialization
> 
> 7,0>    IOMMU Registers and RAM Test
> 
> 7,0>    Streaming Buffer Registers and RAM Test
> 
> 7,0>    SBus Control and Config Registers Test
> 
> 7,0>    SysIO RAM Initialization
> 
> 7,0>Board 3 SysIO Functional Test
> 
> 7,0>    Clear Interrupt Map and State Registers
> 
> 7,0>    SysIO Interrupts  Test
> 
> 7,0>    SysIO Timers/Counters Test
> 
> 7,0>    IOMMU Virtual Address TLB Tag Compare Test
> 
> 7,0>    Streaming Buffer Flush Test
> 
> 7,0>    DMA Merge Buffer Test
> 
> 7,0>    SYSIO ECC Correctable Test
> 
> 7,0>    SYSIO ECC UnCorrectable Test
> 
> 7,0>    SysIO Sbus Probe Test
> 
> 7,0>    SysIO Register Initialization Test
> 
> 7,0>    SysIO RAM Initialization Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0>Board 3 OnBoard IO Chipset (SOC) Test
> 
> 7,0>    SOC SRAM Test
> 
> 7,0>    SOC Registers Test
> 
> 7,0>    SOC Interrupt Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0> TESTING SysIO Port 1
> 
> 7,0>Board 3 SysIO Registers Test
> 
> 7,0>    SysIO Register Initialization
> 
> 7,0>    IOMMU Registers and RAM Test
> 
> 7,0>    Streaming Buffer Registers and RAM Test
> 
> 7,0>    SBus Control and Config Registers Test
> 
> 7,0>    SysIO RAM Initialization
> 
> 7,0>Board 3 SysIO Functional Test
> 
> 7,0>    Clear Interrupt Map and State Registers
> 
> 7,0>    SysIO Interrupts  Test
> 
> 7,0>    SysIO Timers/Counters Test
> 
> 7,0>    IOMMU Virtual Address TLB Tag Compare Test
> 
> 7,0>    Streaming Buffer Flush Test
> 
> 7,0>    DMA Merge Buffer Test
> 
> 7,0>    SYSIO ECC Correctable Test
> 
> 7,0>    SYSIO ECC UnCorrectable Test
> 
> 7,0>    SysIO Sbus Probe Test
> 
> 7,0>    SysIO Register Initialization Test
> 
> 7,0>    SysIO RAM Initialization Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0>Board 3 OnBoard IO Chipset (FEPS) Test
> 
> 7,0>    FAS366 Registers Test
> 
> 7,0>    ESP FAS366 DVMA burst mode read/write Test
> 
> 7,0>    FAS366 FIFO TO DMA Test
> 
> 7,0>    DMA TO FAS366 FIFO Test
> 
> 7,0>    FEPS (Ethernet) Registers Test
> 
> 7,0>    FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test
> 
> 7,0>    SysIO Register Initialization Test
> 
> 7,0>    SysIO RAM Initialization Test
> 
> 7,0>    Clear Interrupt Map and State Registers Test
> 
> 7,0>IO BOARD 3 TESTED
> 
> 7,0>SYSTEM LEVEL TESTING
> 
> 7,0>Board 7 Cache Coherency Test
> 
> 7,0>    Multi-Processor Cache Coherence Test
> 
> 7,0>	Testing CPU MID 18
> 
> 7,0>	Testing CPU MID 19
> 
> 7,0>Probing for Disk System boards
> 
> 7,0>Board 7 System Interrupts Test
> 
> 7,0>    System Interrupts Test
> 
> 7,0>Checking Power Supply Configuration
> 
> 7,0>Power is more than adequate, load 4 ps 3
> 
> 7,0>    Check Board Present Test
> 
> 7,0>    Board Present Interrupt Test
> 
> 7,0>
> 
> 7,0>	System Board Status
> 
> 7,0>-----------------------------------------------------------------
> 
> 7,0> Slot   Board Status     Board Type      Failures
> 
> 7,0>-----------------------------------------------------------------
> 
> 7,0>  0  | Not installed  |             |
> 
> 7,0>  1  | Normal         |+IO Type 4   |
> 
> 7,0>  2  | Not installed  |             |
> 
> 7,0>  3  | Normal         |+IO Type 4   |
> 
> 7,0>  4  | Not installed  |             |
> 
> 7,0>  5  | Not installed  |             |
> 
> 7,0>  6  | Not installed  |             |
> 
> 7,0>  7  | Normal         |+CPU/Memory  |
> 
> 7,0>  8  | Not installed  |             |
> 
> 7,0>  9  | Normal         |+CPU/Memory  |
> 
> 7,0> 16  | Normal         | Clock Board |
> 
> 7,0>-----------------------------------------------------------------
> 
> 7,0>
> 
> 7,0>	CPU Module Status
> 
> 7,0>-----------------------------------------------------------------
> 
> 7,0> MID  OK  Cache  Speed   Version
> 
> 7,0>-----------------------------------------------------------------
> 
> 7,0> 14 | y | 4096  |  336  | 00170011.20000507
> 
> 7,0> 18 | y | 4096  |  336  | 00170011.20000507
> 
> 7,0> 19 | y | 4096  |  336  | 00170011.20000507
> 
> 7,0>-----------------------------------------------------------------
> 
> 7,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
> 
> 7,0>	Populated Memory Bank Status
> 
> 7,0>		bd #	Size	Address	Way	Status
> 
> 7,0>		7	256	0	4	Normal
> 
> 7,0>		7	256	2	4	Normal
> 
> 7,0>		9	256	1	4	Normal
> 
> 7,0>		9	256	3	4	Normal
> 
> 7,0>
> 
> 7,0>
> 
> 	POST COMPLETE
> 
> 7,0>Entering OBP
> 
> 
> ttya initialized
> Using POST's System Configuration
> Setting up memory
> Starting CPU ID 18 
> Starting CPU ID 19 
> Clock board TOD does not match TOD on any IO board.
> fhc  ac  simm-status  environment  sram  flashprom  SUNW,UltraSPARC-II  
> fhc  ac  simm-status  environment  sram  flashprom  SUNW,UltraSPARC-II
> SUNW,UltraSPARC-II  
> Probing UPA Slot at 2,0   sbus  fhc  ac  environment  flashprom  eeprom
> sbus-speed  counter-timer  
> Probing UPA Slot at 3,0   sbus  counter-timer  
> Probing UPA Slot at 6,0   sbus  fhc  ac  environment  flashprom  eeprom
> sbus-speed  counter-timer  
> Probing UPA Slot at 7,0   sbus  counter-timer  
> Evaluating: 
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Received on Fri Feb 22 16:21:32 2002

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